Controlled collapse chip connection (C4) or flip-chip technology has been successfully used for interconnecting high I/O (input/output) count and area array solder bumps on silicon chips to base ceramic chip carriers, for example alumina carriers. In C4 technology or flip chip packaging, one or more integrated circuit chips are mounted above a single or multiple layer ceramic (MLC) substrate or board, and pads on the chip(s) are electrically or mechanically connected to corresponding pads on the other substrate by a plurality of electrical connections, such as solder bumps.
In MLC packages, a ceramic substrate is the platform upon which chips, passive components, protective lids, and thermal enhancement hardware are attached. Wiring patterns within the substrate carrier define escape paths in single chip modules (SCMs) and multichip modules (MCMs), transforming the tight I/O pitch at the die level of the chips to a workable pitch at the board level. The wiring pattern also establishes the modules' power distribution network. Vertical metal vias provide interconnections between the various layers within the MLC. C4 pads can be directly soldered onto MLC vias, providing low inductance, and direct feed to power and ground planes.
One aspect contributing to the non uniformity of the carrier surface is related to a condition referred to as via-bulge. During firing, the expansion/contraction of the typical conductive paste is not the same as that for the typical dielectric material encompassing the vias and etch lines. Therefore, vias which protrude from the surface and that go into the substrate through many layers will tend to form hills on the carrier's mounting surface, and will produce via-bulge. Accordingly, vias need to be jogged every six to eight layers to mitigate via bulge. “Jogging” means that a via includes a bend or transition that is substantially transverse to the via direction between layers. For example, a vertical metal via that provides interconnections between layers is typically jogged horizontally along a “redistribution layer” to a location spaced from the vertical metal via. A new via is provided which then can continue vertically to one or more additional layers spaced below the redistribution layer, or the via can be grouped together with one or more other vias to reduce the number of vias for routing to additional layers. The redistribution layer is a layer in which the vias can be jogged and/or grouped together employing conductive lines, so that the vias can be moved to other locations on the redistribution layer, or so that the number of vias can be reduced. The redistribution layers are typically power layers, ground layers and signal layers.
Routing of signal lines through a ceramic substrate begins at a die/package interface where signals, ground and power escape the pin field of a given die. The arrangement of the signal, ground and power pins (or C4s) is a reflection of the logic blocks on the die. Certain logic blocks rely on differential signal line pairs to effectively transmit and receive high speed signals. Therefore, the routing of the differential signal line pairs can be restricted based on a particular connection points specified by the logic blocks, the need to jog every six to eight layers, and the available routing area.